High-speed input/output signaling mechanism using a polling CPU and cache coherency signaling

摘要

Applicant's high-speed input/output signaling mechanism makes exclusive use of one or more processors (CPU) for polling. Device-bound perpetual polling is initiated neither by the device nor by the processing application: it takes place independently from them, on a CPU exclusively reserved for that task. Another aspect of the present invention is that communication with the I/O device is through the use of "DMA descriptors" that reside in the main memory of the system. In an alternative embodiment, a special purpose device that lacks the full architecture of a typical CPU may play the role of the exclusive polling CPU.