发明名称 Preventing the occurrence of unwanted bit patterns in scrambled data
摘要 The apparatus provides for removal of undesirable data sequences for scrambled data prior to transmission to prevent the scrambled data being the same as timing reference signals. Data input is scrambled by a first scrambler 3 and simultaneously passed to data modifier 13 to be modified and then scrambled by a second scrambler 15. The output from the first scrambler is analysed by analysis module 9 to compare it to forbidden data patterns and the result of this analysis is used by control module 11 to select between the output from the first and second scramblers for transmission. The first scrambler output will normally be used for transmission except where the data output from the first scrambler equals a reserved word, such as synchronising pattern, when the output from the second scrambler will be selected for transmission.
申请公布号 GB2430510(A) 申请公布日期 2007.03.28
申请号 GB20050019677 申请日期 2005.09.27
申请人 SNELL & WILCOX LIMITED 发明人 DAVID LYON
分类号 H04K1/00;H04L25/03;H04N7/167 主分类号 H04K1/00
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