发明名称 Modeling a logic design
摘要 Modeling a logic design includes displaying a menu comprised of different types of functional block diagrams, receiving an input selecting one of the different types of functional block diagrams, retrieving a selected functional block diagram, and creating a graphical representation of a logic design using the selected functional block diagram. The graphical representation is created by interconnecting the selected functional block diagram with one or more other functional block diagrams to generate a model of a logic design and defining the selected functional block diagram using simulation code if the functional block diagram is undefined when retrieved.
申请公布号 US7197724(B2) 申请公布日期 2007.03.27
申请号 US20020054179 申请日期 2002.01.17
申请人 INTEL CORPORATION 发明人 WHEELER WILLIAM R.;FENNELL TIMOTHY J.
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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