发明名称 GENERATING A PULSE SIGNAL WITH A MODULATED DUTY CYCLE
摘要 Generating an output pulse signal (Y), which has an output signal period (T<SUB>y</SUB>), which is divided by a magnitude transition into a leading part (LP) and a trailing part (TP). During each output signal period (T<SUB>y</SUB>) altering means (27 to 36) determine in a coarse and fine way a duration (T<SUB>LP</SUB>, T<SUB>TP</SUB>) of one or both of said output signal period parts (LP, TP) by using a clock signal (Cx) of different clock cycle durations (T<SUB>Cx0</SUB>, T<SUB>Cx1</SUB>, T<SUB>Cx2</SUB>), dependent on a value of a first digital number (Dl) and a value of a second, less significant digital number (D3, D5), respectively.
申请公布号 WO2007031940(A2) 申请公布日期 2007.03.22
申请号 WO2006IB53224 申请日期 2006.09.12
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V.;PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH;DEPPE, CARSTEN;HATTRUP, CHRISTIAN 发明人 DEPPE, CARSTEN;HATTRUP, CHRISTIAN
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