Integrated circuit comprising a UV erasure protected memory

摘要

The circuit has a memory (MEM1) containing transaction data, with electrically erasable and programmable memory cells (C i, j) arranged in horizontal and vertical lines, and linked to word lines (WL i) and bit lines (BL j). A control unit (CTU) executes commands for reading or writing in the memory. The CTU is blocked when reference memory cells of one of the groups contain bits of equal value and if the value is different from a value expected for the one of the groups. The CTU controls a voltage generator (VGEN) which supplies a read voltage (Vread) and an erase-programming voltage (Vpp). An independent claim is also included for a method for protecting an integrated circuit against a global data erasure.