发明名称 Clock distribution circuit
摘要 <p>A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit (2) that transmits a clock signal and an amplitude amplification buffer circuit (1) that amplifies the amplitude of cross-coupling connections inserted in parallel with the transmission buffer circuit (2) on a transmission path for the clock signal. Wherein the number of transistors having the same conductivity type as the transistors of a differing conductivity type of the transmission buffer circuit (2) and that of the transistors of a differing conductivity type of the amplitude amplification buffer circuit (1) are the same. At least one transistor is provided as a bias adjustment transistor for adjusting bias in each of the transmission buffer circuit (2) and the amplitude amplification buffer circuit (1), respectively, and bias adjustments are made simultaneously.</p>
申请公布号 EP1764670(A1) 申请公布日期 2007.03.21
申请号 EP20060251520 申请日期 2006.03.22
申请人 FUJITSU LIMITED 发明人 KANDA, KOUICHI;TAMURA, HIROTAKA;YAMAGUCHI, HISAKATSU;OGAWA, JUNJI
分类号 G06F1/10 主分类号 G06F1/10
代理机构 代理人
主权项
地址