| 摘要 |
A first bus 11 and a second bus 12 are connected through a bus repeater 13 having a buffer memory, and DMA (Direct Memory Access) controllers 22, 27 are respectively connected to the buses 11 and 12. The bus repeater 13 can issue DMA request to the respective DMA controllers 22, 27, and these DMA requests can be masked by respective CPUs 22, 27. The DMA controller 22 carries out DMA transfer of data on the bus 11 between the DMA controller 22 and the buffer memory within the bus repeater 13, and the DMA controller 27 carries out DMA transfer between the buffer memory and the bus 12. The CPU 22 masks DMA request of the bus repeater 13 to directly access the buffer, thereby making it possible to check DMA function. Thus, debugging of the system for carrying out DMA transfer through buffer between different buses is easily carried out. <IMAGE> |
