| 摘要 |
PROBLEM TO BE SOLVED: To improve a visibility of failure mark in failure mark formation after an electrical measuring of wafer. SOLUTION: The device is structured by arranging a plating frame 4 of severalμm in width and severalμm in height along a dicing line 3 between a semiconductor chip 2 and chip adjacent to this; ink can be prevented from flowing out to an adjacent chip, even when a large amount of ink is supplied to a surface of the semiconductor chip 2 at failure mark forming time by employing the above-mentioned structure; and the visibility for distinguishing a quality product chip and failure product chip can be improved. COPYRIGHT: (C)2007,JPO&INPIT
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