发明名称 Redundancy circuits hardened against single event upsets
摘要 A decision block is incorporated into a circuit design to provide hardening against single event upset and to store data. The decision block includes a storage element that stores data as long as inputs to the decision block remain constant. The decision block receives a first data input and second data input from redundant logic blocks or from logic blocks designed to provide complementary outputs. The decision block provides an output that is at a same logic level as the first data input if the two data inputs are at expected logic levels during normal operating conditions (i.e., no disturbances). The decision block provides an output that is at a same logic level as a previous output of the decision block if the two data inputs are not at expected logic levels during normal operating conditions.
申请公布号 US2007052442(A1) 申请公布日期 2007.03.08
申请号 US20050219369 申请日期 2005.09.02
申请人 HONEYWELL INTERNATIONAL INC. 发明人 FULKERSON DAVID E.
分类号 H03K19/007 主分类号 H03K19/007
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