发明名称 IMPROVED GATE ELECTRODE SILICIDATION PROCESS
摘要 <p>A fully-silicided gate electrode is formed from silicon and a metal by depositing at least two layers of silicon (130, 131) with the metal layer (155) therebetween. One of the silicon layers (131) may be amorphous silicon whereas the other silicon layer (130) may be polycrystalline silicon. The silicon between the metal layer (155) and the gate dielectric (120) may be deposited in two layers having different crystallinities. This process enables greater control to be exercised over the phase of the silicide resulting from this silicidation process.</p>
申请公布号 WO2007025564(A1) 申请公布日期 2007.03.08
申请号 WO2005EP10457 申请日期 2005.08.29
申请人 FREESCALE SEMICONDUCTOR, INC.;KAUSHIK, VIDYA;FROMENT, BENOIT 发明人 KAUSHIK, VIDYA;FROMENT, BENOIT
分类号 H01L21/8238;H01L21/28 主分类号 H01L21/8238
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