发明名称 METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS
摘要 <p>A method for modifying an upper layout for an upper layer of an IC using information of a lower layout for a lower layer of the IC, the method including (2205) receiving the upper layout containing features and modifications to features, (2215) producing a density map of the lower layout having geometry coverages of sub-regions of the lower layout, (2220) selecting a feature in the upper layout, (2225) retrieving, from the density map, the geometry coverage of a sub-region below the feature, (2230) determining a vertical deviation of the feature using the geometry coverage, (2235) determining an alteration to the modification using the vertical deviation, (2240) applying the alteration to the modification and (2245) repeating for all features.</p>
申请公布号 EP1759321(A2) 申请公布日期 2007.03.07
申请号 EP20050740549 申请日期 2005.04.29
申请人 CADENCE DESIGN SYSTEMS, INC. 发明人 SCHEFFER, LOUIS, K.;TEIG, STEVEN
分类号 G06F17/50;G03F1/36 主分类号 G06F17/50
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