| 摘要 |
A Trellis decoder in which a demodulated signal is handled by dividing into four areas for eight symbols, namely a pre-circuit obtains a 3-bit sign according to a high-order 4-bit sign in the demodulated signal; an area determining circuit identifies any of the four areas by obtaining a 2-bit sign in the 3-bit output from the pre-circuit; a delay circuit delays the 2-bit output from the area determining circuit and a sign for the MSB in the demodulated signal; and a selection circuit identifies a value of a high-order two bits in a received symbol according to the 2-bit output of the area determining circuit, the MSB in the demodulated signal, and an estimated value of the LSB in the received symbol outputted by a convolutional coder. |
