发明名称 Methods of forming integrated circuit devices having metal interconnect layers therein
摘要 Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.
申请公布号 US2007045123(A1) 申请公布日期 2007.03.01
申请号 US20050216686 申请日期 2005.08.31
申请人 HONG DUK H;LEE KYOUNG W;NAUJOK MARKUS;KNOEFLER ROMAN 发明人 HONG DUK H.;LEE KYOUNG W.;NAUJOK MARKUS;KNOEFLER ROMAN
分类号 C25D5/02 主分类号 C25D5/02
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