| 摘要 |
A processor carrying out the present invention is initially issuing instructions in a normal-execution mode (i.e. in program order). If, while executing a program, the processor encounters a launch condition caused by an instruction (a "launch instruction"), it enters speculative-execution mode. While in this mode, the system checks status indicators associated with a forward progress buffer. If these status indicators show that the forward progress buffer contains data for the instruction that caused the launch condition, the system resumes normal-execution mode. Upon resumption of normal-execution mode, the system retrieves the data from a data field contained in the forward progress buffer and executes the launch instruction using the retrieved data as input data for the launch instruction. The system next deasserts the status indicators. The system then continues to issue instructions for execution in program order in normal-execution mode. Using the forward progress buffer in this way prevents the processor from entering a potential live-lock state. The launch condition could be caused by a cache miss (either L1 or Translational Look-aside Buffer, TLB), or because the launch instruction is a divide instruction. |
