SEMICONDUCTOR STORAGE DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a semiconductor storage device in which the test technique and redundancy technology can be optimized at a high level. SOLUTION: An array control circuit 12 is provided which interrupts an operation of a defective element by preventing a word line state signal WLE from being received based on a signal HITL or HITR for determining whether row redundancy replacement is performed. The word line state signal is input to a plurality of memory blocks 11A-0 to 11A-31 and 11B-0 to 11B-31 in cell array units 11A and 11B via a single signal line 13-1. A signal having redundancy information is locally decoded, thereby making it possible to increase the number of arrays which are simultaneously activated and thereby reduce a test period. COPYRIGHT: (C)2007,JPO&INPIT