| 摘要 |
A clock signal driver and a clock signal supplying circuit having the same are provided. An embodiment of the clock signal driver includes an internal clock driver for receiving a clock signal and a complementary clock signal, buffering the clock signal and inverting the complementary clock signal, and combining phases of the buffered clock signal and the inverted complementary clock signal to generate an internal clock signal. And the clock signal driver further includes a complementary internal clock driver for receiving the clock signal and the complementary clock signal, inverting the clock signal and buffering the complementary clock signal, and combining phases of the inverted clock signal and the buffered complementary clock signal to generate a complementary internal clock signal.
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