| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a semiconductor wafer capable of raising an integration degree and a yield of a semiconductor chip region, while ensuring a desired inspection precision. <P>SOLUTION: A plurality of semiconductor chip regions, a first scribing region 80 formed along a primary direction (Y direction) and a second scribing region formed along a secondary direction (X direction) which perpendicularly intersects the primary direction classify the plurality of the semiconductor chip regions and cross in an intersection region. The first scribing region 80 is divided into a first region 88 and a second region 89 by a virtual line 92 parallel to the primary direction. A width of the first region 88 is broader than that of the second region 89. The first scribing region 80 has an alignment mark region 60. In the alignment mark region 60 there is arranged an alignment mark 65 for specifying at least the secondary direction. The second region 89 has a mark region 62 for inspection. In the second scribing region, a region except the intersection region doesn't have any alignment mark region 60 and any mark region 62 for inspection. <P>COPYRIGHT: (C)2007,JPO&INPIT |
