发明名称 |
Wave pipelined output circuit of synchronous memory device |
摘要 |
Provided is a wave pipelined output circuit of a synchronous memory device. In the wave pipelined output circuit, paths for transferring data in a high frequency mode of the synchronous memory device are separated from paths for transferring the data in a low frequency mode of the synchronous memory device. The number of registers included in data output paths in the high frequency mode is reduced and the number of control signals used for data input/output of the registers is also reduced. Consequently, loads of the data output paths in the high frequency mode are decreased to improve a high frequency operation and reduce the chip area of the output circuit.
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申请公布号 |
US2007043921(A1) |
申请公布日期 |
2007.02.22 |
申请号 |
US20060504897 |
申请日期 |
2006.08.16 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
KIM JOUNG-YEAL;JANG SEONG-JIN |
分类号 |
G06F13/00 |
主分类号 |
G06F13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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