| 摘要 |
The present invention relates to a filter circuit for a set of original data (X 0 -X 7 ) able to implement in series the steps of discrete transformation (DCT 2 ), correction (ZER) of odd transformed data and inverse discrete transformation (IDCT 2 ). The filter circuit takes advantage of the fact that the paths corresponding to the even and odd transformed data are completely separate with the exception of a first processing stage (ST 1 ) of the discrete transformation and a last processing stage (ST 8 ) of the inverse discrete transformation in order to connect a first half of the data issuing from the first stage to the last processing stage. The implementation of the filter circuit is thus simplified, both making the circuit less expensive and giving it a lower power consumption. For optimized implementation, the filter circuit functions in differential mode.
|
