Burst Mode Clock/Data Recovering Circuit with Robustness to Duty Cycle Distortion,申请号KR20050024806-传众专利搜索

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发明名称	Burst Mode Clock/Data Recovering Circuit with Robustness to Duty Cycle Distortion
摘要
申请公布号	KR100684919(B1)	申请公布日期	2007.02.20
申请号	KR20050024806	申请日期	2005.03.25
申请人		发明人
分类号	H03L7/00;H03K5/14	主分类号	H03L7/00
代理机构		代理人
主权项
地址

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