发明名称 |
Six-transistor (6T) static random access memory (SRAM) with dynamically variable p-channel metal oxide semiconductor (PMOS) strength |
摘要 |
In embodiments of the present invention, a static random access memory (SRAM) device has an array of memory cells in columns and rows. An individual memory cell includes two PMOS pull-up devices coupled to two NMOS pull-down devices. In READ mode and/or STANDBY/NO-OP mode of a column, the two PMOS pull-up devices are effectively strengthened by forward biasing the PMOS n-wells or by utilizing a lower threshold voltage PMOS device by implanting a lower halo dose in the PMOS device. In WRITE mode of a column, the two PMOS pull-up devices are effectively weakened by reverse biasing the PMOS n-wells or by coupling the sources of the NMOS devices to virtual ground (V<SUB>SSi</SUB>).
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申请公布号 |
US7177176(B2) |
申请公布日期 |
2007.02.13 |
申请号 |
US20040883609 |
申请日期 |
2004.06.30 |
申请人 |
INTEL CORPORATION |
发明人 |
ZHENG BO;ZHANG KEVIN;HAMZAOGLU FATIH;WANG YIH (ERIC) |
分类号 |
G11C11/00;G11C5/14;G11C7/10 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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