MEMORY BITCELL AND METHOD OF USING THE SAME

摘要

A memory bitcell comprises first (102) and second (103) transistors and a cantilever module (104) having two states. The first transistor (102) is arranged to communicate a first signal to the input of the cantilever module (104) upon receipt of a second signal. The second transistor (103) is arranged to bypass the cantilever module (104) upon receipt of a third signal (RST) . The memory bitcell is operable such that the state of the cantilever (104) can be changed in order to represent one bit of binary information and can be detected by monitoring the first signal.