| 摘要 |
A semiconductor circuit includes a parity bit adding circuit configured to add a parity bit to a data to be read by a CPU; a register configured to hold the data with the parity bit; and a parity check circuit configured to execute a parity check of said data with said parity bit held in said register, and to issue a parity error interrupt when a parity error is detected. A parity bit inverting circuit inverts said parity bit held in said register in response to completion of said parity check.
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