| 摘要 |
PROBLEM TO BE SOLVED: To provide a device and a method for logic verification for an integrated circuit that leads to early finding of a bug in a verification stage of logic system development by checking and displaying differences between a previously registered operation specification description and a separately input operation specification description. SOLUTION: Provided is the device for logic verification which compares the separately input operation specification description with an operation specification description automatically generated from a device generating an operation specification description that a logic system described in a hardware description language and a logic verifying device performing logic verification by deciding equivalence of the operation specification description use. Provided is a means of objectively evaluating the operation specification description by showing deficiency and redundancy of the operation specification description. COPYRIGHT: (C)2007,JPO&INPIT
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