| 摘要 |
An integrated circuit device (for example, logic or discrete memory device) including a memory cell including an electrically floating body transistor, wherein the electrically floating body transistor includes a source region, a drain region, a body region disposed between the source region and the drain region, wherein the body region is electrically floating, and a gate disposed over the body region. The memory cell includes (i) a first data state which is representative of a first charge in the body region of the electrically floating body transistor, and (ii) a second data state which is representative of a second charge in the body region of the electrically floating body transistor. Circuitry, coupled to the electrically floating body transistor of the memory cell, (i) generates read control signals to perform a read operation of the memory cell and (ii) apply the read control signals to the electrically floating body transistor to sense the data state of the memory cell; wherein, in response to read control signals, the electrically floating body transistor replenishes charge in the body region of the electrically floating body transistor during the read operation. The electrically floating body transistor may be disposed on a bulk-type substrate or SOI-type substrate.
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