| 摘要 |
An electronic system including an instruction-programmable processor, such as a digital signal processor, having a level one program cache memory and instruction buffer subsystem , is disclosed. The level one program cache memory and instruction buffer subsystem includes a program data random access memory (RAM) (60), in combination with a tag RAM (54) and a tag comparator (52), and a loop cache subsystem (62) in parallel with the program data RAM (60). An instruction fetch unit presents fetch addresses to the tag comparator (52) and to the loop cache subsystem (62). The loop cache subsystem (62) includes a branch cache register file for storing instruction opcodes corresponding to a sequence of fetch addresses beginning with a base address. If the fetch address issued by the instruction fetch unit is a hit relative to the loop cache subsystem (62), loop cache control logic disables reads from the program data RAM (60) in favor of accesses to the branch cache register file. According to one disclosed embodiment, the branch cache register file is loaded with opcodes beginning with each backward branch that is a miss relative to the branch cache register file. According to another disclosed embodiment, the branch cache register file is loaded with opcodes beginning with backward branches that are a miss relative to the branch cache register file and that have been executed twice in succession. <IMAGE> |
