发明名称 PROCESS FOR FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
摘要 When probe-mark inspection is performed using a probe card equipped with a thin film probe, a visual inspection system (51) visually inspects an external view of the major surface of an inspection object, i.e. a wafer, collects inspection results such as adhesion of a dust particle to the major surface of the wafer or abnormal shape of a bump electrode on the major surface of the wafer, as wafer map data in the order of arrangement of respective chips in the wafer plane. The wafer map data is transmitted through a server (52) to a probe inspection system (53) where probe-mark inspection is omitted for the chips which have not passed visual inspection according to the wafer map data and probe-mark inspection is performed for the other chips which have passed visual inspection. ® KIPO & WIPO 2007
申请公布号 KR20070015222(A) 申请公布日期 2007.02.01
申请号 KR20067025992 申请日期 2006.12.08
申请人 RENESAS TECHNOLOGY CORP. 发明人 KANDA MAKOTO;WATANABE KOJI;HIROTA DAISUKE
分类号 H01L21/66;G01R1/067 主分类号 H01L21/66
代理机构 代理人
主权项
地址