| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technology for enhancing packaging performance of a semiconductor device. <P>SOLUTION: A package substrate 3 having a plurality of lands 3d of NSMD structure, and a take-out wiring 3i and dummy wiring 3j connected with the plurality of lands 3d, respectively, and arranged at positions of 180° symmetry is prepared. Since solder is printed on the plurality of lands 3d by printing method after a package is assembled, variation in height of solder coat can be reduced between lands and thereby packaging performance of LGA (semiconductor device) 7 is enhanced. <P>COPYRIGHT: (C)2007,JPO&INPIT |
