| 摘要 |
<p>A method for fabricating a high-voltage PMOS transistor is provided to eliminate the necessity of two photolithography processes and two masks by mixing a first triple N-well process with a deep N-well process and by mixing a field stop ion implanting process with an N-well process of a low-voltage PMOS transistor. A P-type semiconductor substrate is prepared which includes a high-voltage PMOS transistor region, a low-voltage PMOS transistor region and a cell region. A deep N-well is formed in the cell region and the high-voltage PMOS transistor region. A retrograde N-well is formed in a field region of the high-voltage PMOS transistor region and in the low-voltage PMOS transistor region, including an ion implantation layer, a punch-through ion implanting layer and a channel stop ion implanting layer. An ion implantation layer for adjusting a threshold voltage is formed in the high-voltage PMOS transistor region. An isolation layer is formed in the semiconductor substrate in a field region. A gate is formed on a predetermined region of the substrate. A DDD(double doped drain) junction is formed in the substrate at both sides of the gate. An interlayer dielectric is formed on the resultant structure, and a contact hole for exposing the DDD junction is formed in the interlayer dielectric. An ohmic contact layer is formed in the DDD junction under the contact hole. The ion implantation energy for forming the punch-through ion implanting layer and the channel stop ion implanting layer is set at 150~250 kilo electron volts.</p> |
