| 摘要 |
A semiconductor memory device is provided to achieve large capacity of a memory while reducing power consumption in a standby mode and an operation mode, by arranging one source line per two adjacent rows of memory cells. In a semiconductor memory device(100) with memory cells(111) arranged in a matrix. The memory cell is constituted with one transistor. A word line is arranged correspondingly to each row of the matrix, and is connected to a gate port of each transistor in a corresponding row in common. A bit line is arranged in correspondence to each column of the matrix, and is connected to a drain port of at least one transistor of a corresponding column in common. A source line is arranged correspondingly to two adjacent rows of the matrix, and is connected to a source port of each transistor of the two rows in common. A precharge circuit precharges the bit line with a precharge potential correspondingly to a precharge signal indicating t period of precharging the bit line. A precharge signal generation circuit generates the precharge signal. A source bias control circuit controls at least one of source lines not connected to a memory cell to be read, under the state that a source bias potential higher than a ground potential and lower than a power supply potential is supplied during an active period for reading data from the memory cell.
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