发明名称 |
Methods of screening ASIC defects using independent component analysis of quiescent current measurements |
摘要 |
A method and computer program for screening defects in integrated circuit die includes steps of receiving as input measurements of quiescent current for each die in a sample lot of semiconductor die and generating a test matrix from the quiescent current measurements for each die in the sample lot. A de-mixing matrix is computed from independent component analysis that models passing die in the sample lot. A matrix of sources is generated as a product of the test matrix and the de-mixing matrix. The matrix of sources is normalized to zero mean and unit variance. A statistical limit of the passing die in the sample lot is selected from each of the sources in the normalized matrix of sources to determine a maximum and a minimum quiescent current limit for each of the sources. The maximum and the minimum quiescent current limit for each of the sources is generated as output.
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申请公布号 |
US7171638(B2) |
申请公布日期 |
2007.01.30 |
申请号 |
US20040969745 |
申请日期 |
2004.10.20 |
申请人 |
LSI LOGIC CORPORATION |
发明人 |
TURAKHIA RITESH P.;BENWARE ROBERT B. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
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