发明名称 |
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack |
摘要 |
A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.
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申请公布号 |
US2007020805(A1) |
申请公布日期 |
2007.01.25 |
申请号 |
US20060528986 |
申请日期 |
2006.09.27 |
申请人 |
KIM SARAH E;LIST R S;LETSON TOM |
发明人 |
KIM SARAH E.;LIST R. S.;LETSON TOM |
分类号 |
H01L21/00;H01L21/768;H01L23/48;H01L25/065 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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