| 摘要 |
A non-volatile semiconductor memory is provided to increase an operation speed of a memory cell transistor and improve integration by forming a metal salicide layer only under each device and a gate contact of a wordline. A cell array region is constructed to include a memory cell transistor. The memory cell transistor includes a first/drain region, a gate insulation layer formed on a semiconductor region between the first source region and the first drain region, a first floating gate electrode formed on the gate insulation layer, and a first control gate electrode stacked on the first floating gate electrode through a first intergate dielectric. A circuit region is constructed to include a transistor. The transistor includes an isolation region, a second source/drain region isolated by the isolation region, a gate insulation layer formed on a semiconductor region between the second source region and the second drain region, a second floating gate electrode formed on the gate insulation layer, a second intergate dielectric with an opening formed on the second floating gate electrode, a second control gate electrode formed on the second intergate dielectric, a metallic salicide layer(11) formed on the second control gate electrode, and a gate contact in electrical contact with the metallic salicide layer. The metallic salicide layer is formed only under the gate contact.
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