| 摘要 |
<P>PROBLEM TO BE SOLVED: To reduce a field concentration between wiring caused by microfabrication, and to improve reliability. <P>SOLUTION: Bit lines BL 1e, BL 1o, BL 2e, and BL 2o on a wiring layer M1 are arranged with minimum widths and spaces in a chip. Potential difference V1 at the maximum is given between the bit lines. A minimum space is a value which assures that no wiring short circuit may be caused by dielectric breakdown when the potential difference V1 is given between the bit lines. This value may be a minimum processing dimension available in a design rule or lithography. Although potential difference V2 (>V1) is given between shield supply lines BLSHIELD and the bit lines on the wiring layer M1, the shield supply lines BLSHIELD on the wiring layer M1 are sufficiently separated from a region where the bit lines are arranged at minimum spaces. <P>COPYRIGHT: (C)2007,JPO&INPIT |
