| 摘要 |
PROBLEM TO BE SOLVED: To reduce inter-bit line noise and array noise, a sense amplifier area, and power consumption of an array during an operation without increasing a memory cell block size in an FRAM. SOLUTION: In the FRAM where a plurality of memory cells having ferroelectric capacitors connected in parallel to a transistor are serially connected to constitute a cell block and arrayed in a matrix to constitute a memory cell array 10, a sense amplifier circuit 14 is arranged in a row-direction one end side for every four cell blocks (101 to 104) sequentially adjacent to one another in a row direction, one end each of the four cell blocks is connected to first to fourth bit lines (/BL0, /BL1, BL0 and BL1) via block selection transistors (121 to 124) while each of the other ends is correspondingly connected to plate lines (/PL0, PL0, and PL1). The first bit line /BL0 and the third bit line BL0 form a first bit line pair, and the second bit line /BL1 and the fourth bit line BP1 form a second bit line pair. COPYRIGHT: (C)2007,JPO&INPIT |
