发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH MUTING CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a muting circuit which detects power-off in an internal circuit when the power is turned off and automatically makes a circuit in a muting state by suppressing DC difference in level of occurrence when performing switching between muting state/non-muting state. SOLUTION: A MOS transistor is used as a muting transistor to thereby suppress voltage fluctuation of a muting transistor terminal when switching to a muting state in a built-in muting circuit since saturation voltage becomes large in the manufacturing process of a semiconductor integrated circuit. Additionally, an external capacitor element 26 is connected to the connection point of resistors 38 and 39 between a VCC and a GND terminal inside the semiconductor integrated circuit, and 1/2 VCC signal is made to fall slowly when the power is turned off to thereby turn on the MOS transistor 23, increasing gate voltage the muting transistor (MOS transistor 21) and turning on the MOS transistor 21. Thus, bias fluctuation is suppressed when the power is off and output fluctuation of an amplifier 27 is suppressed when the internal circuit is turned off. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007019948(A) 申请公布日期 2007.01.25
申请号 JP20050200161 申请日期 2005.07.08
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 KAKUMOTO YASUNOBU;FUJII KEIICHI
分类号 H03F1/00 主分类号 H03F1/00
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