| 摘要 |
PROBLEM TO BE SOLVED: To obtain an architecture verification apparatus capable of easily correcting a hardware model. SOLUTION: Each of hardware models 200a, 200b performs simulation based on description indicating the operation, data processing unit and timing of hardware. As the description, algorithm operation description 211, data access description 212 and timing generation description 213 are separately constituted. Consequently, the correction of operation description is not required for the change of a data processing unit and the change of operation timing. COPYRIGHT: (C)2007,JPO&INPIT
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