| 摘要 |
A data training circuit is provided to control data setup and hold time of a clock by optimizing the setup time and the hold time regardless of data skew generated due to a data channel between a chip set and a memory device, a signal root and wire bonding in the memory device. A first receiver part(110) receives data. A decoder(120) decodes an address signal, and outputs a period signal whose level is shifted with a first period and a data selection signal to select data. A control part(130) is enabled in response to the data selection signal, and outputs a delay control signal for controlling a delay period of the data in response to the period signal, and a plurality of phase mixing control signals. A first delay part(150) outputs first delay data by delaying the data outputted from the first receiver part as long as a first delay section. A second delay part(160) outputs second delay data by delaying the data outputted from the first receiver part as long as a second delay section. A delay control part(140) controls the first delay section and the second delay section, in response to the input of the delay control signal. A phase mixer(170) receives the first delay data and the second delay data, and mixes the phases of the first delay data and the second delay data at a mixing ratio determined by the assembly of the phase mixing control signals.
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