发明名称 SEMICONDUCTOR MEMORY APPARATUS
摘要 PROBLEM TO BE SOLVED: To detect easily minute leak of a bit line without increasing chip size of a semiconductor memory apparatus. SOLUTION: An equalizing circuit connects a pair of bit lines each other, while connects the pair of bit lines to a pre-charge voltage line, in response to activation of an equalization control signal. An equalization control circuit makes the equalization control signal non-activation in response to activation of a first timing signal. A word line drive circuit activates any line of word lines in response to activation of a second timing signal. A first signal generating circuit of a timing control circuit generates the first timing signal. A second signal generating circuit of the timing control circuit activates the second timing signal after non-activation of the equalization control signal as activation of the first timing signal. A delay control circuit of the second signal generating circuit delays activation timing of the second timing signal more than that at the time of a normal mode at the time of a test mode. COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007012141(A) 申请公布日期 2007.01.18
申请号 JP20050190298 申请日期 2005.06.29
申请人 FUJITSU LTD 发明人 IKEDA HITOSHI;MORI IKU;OKUYAMA YOSHIAKI
分类号 G11C29/04;G11C11/401;G11C11/409 主分类号 G11C29/04
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