| 摘要 |
A data processor apparatus and memory interface comprises a memory, a plurality of memories, an interface for controlling access to the memories by a device, and an identifier identifying at least a memory location in one memory and a memory location in another memory. The interface is responsive to the identifier to condition the memory locations for receiving data and/or for transferring data therefrom. This arrangement eliminates the need for a dedicated broadcast bus from the array controller to each PU, which thereby enables the area/space required to accommodate the data processor to be significantly reduced.
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