| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To disclose a cap for a semiconductor device package capable of via-hole plating having a seed layer while forming a cavity. <P>SOLUTION: The cap for a semiconductor device package includes a body having a cavity and a predetermined thickness, a first via-hole formed so as to have a predetermined depth from the cavity formation surface of a substrate, a first seed layer formed on the inner circumferential surface of the first via-hole, a second via-hole formed so as to have a predetermined depth from the opposite surface of the cavity of the substrate, a second seed layer formed on the inner circumferential surface of the second via-hole, and a plating material with which the first via-hole and the second via-hole are filled. <P>COPYRIGHT: (C)2007,JPO&INPIT</p> |
