发明名称 SUBSTRATE FOR PLL CIRCUIT FORMATION
摘要 <P>PROBLEM TO BE SOLVED: To reduce the size/cost of a substrate 21 having a PLL circuit 1 formed thereon. <P>SOLUTION: An area Z for PLL circuit formation where a PLL circuit 1 is formed and a sacrificed plate area X which is an area adjacent to the area Z and is cut away after circuit operation examination of the PLL circuit 1 are set on a substrate 20 for PLL circuit formation. A control voltage detecting conductive line 16 for detecting a control voltage is provided to the sacrificed plate area X from a halfway part of a conductive line for a control voltage, which reaches a control voltage input part 7 of a voltage controlled oscillator 2 from an oscillator control circuit 3 of the PLL circuit 1 in the area Z for PLL circuit formation through a loop filter 4. The sacrificed plate area X is provided with an electrode pad part 18 for control voltage measurement connecting with the control voltage detecting conductive line. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2007006124(A) 申请公布日期 2007.01.11
申请号 JP20050183692 申请日期 2005.06.23
申请人 MURATA MFG CO LTD 发明人 FURUKUBO MASASHI;MIURA MASAYA
分类号 H03L7/08;H05K1/11 主分类号 H03L7/08
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