| 摘要 |
A memory layer sequence comprising a lower confinement layer ( 2 ), a charge-trapping layer ( 3 ), and an upper confinement layer ( 4 ) is applied on the main surface of a silicon substrate ( 1 ). By a photolithography step, trenches running parallel at a distance from one another are etched to delimitate the active area. A trench filling ( 7 ) is applied by growth or deposition of dielectric material or by a selective oxidation of the substrate material. After the removal of the charge-trapping layer sequence in a peripheral area and the deposition of a gate dielectric material provided for the transistors of an addressing circuitry, wordline stacks ( 8 ) are formed.
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