According to one embodiment, a memory controller is disclosed. The memory controller includes assignment logic, a reorder table and a transaction assembler. The assignment logic receives a request to access a memory channel and assigns the request to access one of two or more independently addressable subchannels within the channel. The reorder table includes two or more table elements. Each table element includes a shared address component and an independent address component corresponding to each of the two or more independently addressable subchannels. The transaction assembler combines the shared and independent address components in a reorder table element and issue a single memory transaction.
申请公布号
WO2007002552(A2)
申请公布日期
2007.01.04
申请号
WO2006US24729
申请日期
2006.06.23
申请人
INTEL CORPORATION;AKIYAMA, JAMES;CLIFFORD, WILLIAM;BROWN, PAUL