| 摘要 |
A system and method are provided for producing two asymmetric duty cycle clock phases as outputs, where the duration of the active phase may be varied to generate clock signal having an asymmetric duty cycle. A circuit configured according to the invention includes a monostable clock generator configured to produce an asymmetric duty cycle clock phase from a reference clock input, a delayed phase generator configured to produce two clock phases whose falling edges are delayed with respect to the input signals, and a second phase generator configured to produce a second asymmetric duty cycle clock phase. The phase may be programmable by including a variable resistor network that can be varied in response to control signals.
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