| 摘要 |
An apparatus includes an instruction decoder, at least one control register coupled to the instruction decoder, and an add-compare-select (ACS) engine coupled to the at least one control register. The instruction decoder is operative to control the ACS engine to perform Viterbi decoding in response to the instruction decoder receiving a first instruction, and is operative to control the ACS engine to perform turbo decoding in response to the instruction decoder receiving a second instruction.
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