| 摘要 |
Interconnect vias and associated methods of formation are disclosed. One such method includes forming an operable microelectronic feature in a substrate, with the substrate having a first surface and a second surface facing away from the first surface. The method can further include forming a via in the substrate at a process temperature of less than 173K, with the via extending into the substrate from the first surface. A conductive material can be disposed in the via to be in electrical communication with a bond site of the substrate. The microelectronic feature can be coupled to the bond site. In other embodiments, the process can include controlling an angle of sidewalls of the via, and/or forming the via in a single, generally continuous process, in addition to, or in lieu of, forming the via at cryogenic temperatures. |
