发明名称 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, LAYOUT DESIGNING METHOD THEREFOR AND ELECTRONIC COMPONENT MOUNTING SUBSTRATE
摘要 <P>PROBLEM TO BE SOLVED: To effectively solve the problem of a decline in internal supply voltage level by voltage drop in an interconnection while considering the effective use of a free space and a low power consumption of a circuit, in a large-scale semiconductor integrated circuit device. <P>SOLUTION: In this semiconductor integrated circuit device, such a circuit configuration is employed that the internal supply voltage is supplied from both outside and inside of a semiconductor chip 1. The internal supply voltage supplied from outside is via an internal power supply pad 10, while the one supplied from inside is via a regulator 110. The regulator 110 is located at a place where the internal supply voltage level is remarkably dropped by a voltage drop of an internal power supply interconnection 21a, to make up for deficiencies in internal supply voltage which is not just enough only from the internal power supply pad 10. <P>COPYRIGHT: (C)2007,JPO&INPIT
申请公布号 JP2006351633(A) 申请公布日期 2006.12.28
申请号 JP20050172737 申请日期 2005.06.13
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 AOKI NAOAKI
分类号 H01L21/82;H01L21/822;H01L27/04 主分类号 H01L21/82
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