DIRECT FREQUENCY SYNTHESIZER

摘要

A direct frequency synthesizer is provided to enlarge a timing margin of a multiplexer by adjusting a duty ratio of multi-phase clock to be applied to the multiplexer, thereby reducing an influence of process change. A duty adjusting unit(110) adjusts a duty ratio of multi-phase clock signal to be input. A multiplexer(120) selects and outputs one of the multi-phase clock signals output from the duty adjusting unit in response to a clock selection signal to be input. A flip-flop(150) reverses a signal input via a data input terminal(D) in response to the signal output from the multiplexer. The duty adjusting unit has plural two-input END gates receiving two selected clock signals.