发明名称 |
Encoder and decoder circuits for dynamic bus |
摘要 |
A dynamic bus architecture is provided. This may include an encoding circuit coupled to a bus line and a decoder circuit coupled to the bus line. The encoder circuit may receive an input signal and generate an encoded signal on the bus line. The decoder circuit may receive the encoded signal from the bus line and generate the original unencoded signal. The encoder circuit may include a first flip-flop circuit to store a previous input signal from the bus line based on a clocking signal from the bus line. Additionally, the decoder circuit may include a second flip-flop circuit having a clock input to receive the encoded signal from the bus line as a clocking input.
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申请公布号 |
US7154300(B2) |
申请公布日期 |
2006.12.26 |
申请号 |
US20030744084 |
申请日期 |
2003.12.24 |
申请人 |
INTEL CORPORATION |
发明人 |
ANDERS MARK A.;KAUL HIMANSHU;KRISHNAMURTHY RAM |
分类号 |
H03K19/0175;G06F13/00;G11C7/00;H04L25/02 |
主分类号 |
H03K19/0175 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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